1. Field of the Invention
The present invention relates to a large-scale integrated (LSI) circuit utilizing an SOI (Silicon on Insulator) substrate, and in particular relates to an LSI circuit having an ESD (Electro-Static Discharge) protection device.
2. Description of the Related Art
In a typical semiconductor integrated circuit, an ESD protection circuit is provided across an internal circuit and an input terminal (PAD) of the semiconductor integrated circuit, thus preventing an excess electric current flow to the internal terminal when an ESD surge is applied from the input terminal. When a voltage applied to the internal circuit or an electric current flowing to the internal circuit is larger than a predetermined value, an excess electric current instantaneously flows to the ESD protection circuit. Thus, the ESD protection circuit is designed so as to prevent a breakdown of the internal circuit. There have been proposed several ESD protection circuits each having a metal oxide semiconductor FET (MOSFET) formed on an SOI substrate.
Japanese Patent Kokai No. 2002-76131 (document D1) discloses a technology of forming an R-C circuit utilized for triggering an electrostatic discharge protection. The R-C circuit includes a trench capacitor and a resistive element which are formed in an SOI substrate. The R-C circuit in document D1 is utilized to provide a time constant of the trigger operation.
Japanese Patent Kokai No. 2002-324842 (document D2) discloses a semiconductor protection circuit having an NMOS as a protection device for protecting an SOI semiconductor circuit from ESD. In document D2, a PMOS is conductive at a time when a stress of the ESD is applied, and thus a positive voltage is applied onto a semiconductor substrate. Owing to a substrate bias effect, a threshold voltage of the NMOS is decreased and a trigger voltage having a snapback characteristic is decreased. In document D2, it is suggested that the PMOS may be replaced by a capacitor.
Japanese Patent Kokai No. 2006-86239 (document 3) discloses a semiconductor device including a layered substrate, a removed part, a cavity part, an ESD protection circuit and a semiconductor element. The layered substrate has a plurality of regions which are overlaid with each other. Upper parts of a semiconductor layer, an insulating layer, and a bulk layer, formed in a first region of the layered substrate are removed so as to form the removed part. An upper part of a bulk layer of a second region adjacent to the removed part is removed so as to form the cavity part. The ESD protection circuit is formed on the bulk layer of the removed part. The semiconductor element is formed in at least one part of the second region of the semiconductor layer. The document D3 states to form an ESD protection circuit which effectively functions for a semiconductor device having an SOI structure having a silicon layer with a thin thickness.
Japanese Patent Kokai No. 2005-93802 (document D4) discloses a method of modeling electric characteristics of an ESD protection device, which method is utilized for simulating a circuit including an ESD protection device. The method includes a parameter configuration step and a modeling step. In the parameter configuration step, at least one specific parameter, which will influence the electric characteristics of the ESD protection device, is configured. In the modeling step, the electric characteristics of the ESD protection device are modeled on the basis of the specific parameter. Accordingly, a change in characteristics of the ESD protection device can be easily expected or evaluated.
A document entitled “ESD protection for SOI technology using under-the-BOX (substrate) diode structure”, A. Salman et al., AMD, EOS/ESD symp., 4B.2, 2004 (document 5) suggests that an ESD protection circuit formed on an SOI substrate is thermally damaged by an increased temperature due to a self-heating because the ESD is surrounded by an insulating film of low thermal conductivity. Document 5 also suggests that a breakdown voltage and electric consumption (I: surge electric current×surge voltage) contributing the heat generation should be decreased. In order to lower the breakdown voltage, a method of increasing a substrate electric potential Vsub during an operation of an ESD protection circuit is described to be effective in document D2.
However, for the purpose of preventing destruction of an ESD protection circuit, it is desirable not only to lower the breakdown voltage but also to enhance a durability against thermal destruction that is caused by a higher electric consumption.